TIME OPTIMIZED PROGRAMMABLE MEMORY BUILT-IN SELF TEST FOR EMBEDDED RAM

Abstract

In the embedded technology today, memories are the universal components. ROM, SRAM, DRAM or flash memory, any one or a combination can be found in almost all system chips. With the onset of the deep-submicron VLSI technology, the density and capacity of the memory is growing. The wide use of embedded memory forms the basis of emerging new architecture and technologies. However providing a cost effective test solution for these on-chip memories is becoming a challenging task. Memory BIST over the recent times has proven to be one of the cheapest and widely used techniques to perform memory testing.  In this research, FSM based programmable memory BIST architecture is proposed which can select March algorithms to test the memory. March algorithms are test algorithms used to test memory because of their high fault coverage and less complexity. Experimental results show that the proposed architecture has reduced simulation time, increased work frequency and improved flexibility.