A VHDL Implementation of Low Area Advance Encryption Standard Processor

Abstract

In this work our aim to achieve a high through put compact. AES S-Box with minimum area consumption. To improve architectures are proposed for implementation of S-Box and Inverse S-box needed in the Advanced Encryption Standard (AES). Unlike previous work which rely on look-up table to implement the Subbytes and Invsubbytes transformations of the AES algorithm the proposed design employs Combinational logic only for implementing Subbytes (S-Box) and InvsubBytes (Inverse S Box). The resulting hardware requirements are presented for proposed design and compared by ROM- based and Pre-Computation technique and improve with this two technique a new technique is Galois field arithmetic.