TRENDS AND TRADE-OFFS IN DESIGNING AND PERFORMANCE EVALUATION OF DIFFERENT ON-CHIP AMBA BUS

Abstract

Moore's law predicts that soon it will be possible to integrate billions of transistors on a single chip. Currently on chip communication for multiprocessor system-on-chip (MPSoC) is realized using buses such as AMBA protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs. Modern computer system rely more and more on –chip communication protocol to exchange data. System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as pipelining, burst and split transfers. In this paper, we describe a case study for   different AMBA SOC bus protocol and their performance comparison: the Advanced Micro-controller Bus Architecture (AMBA) protocol from ARM. It starts with a brief introduction AMBA 2.0 protocol, AMBA 3.0 protocol and AMBA 4.0 protocol ,and concludes with a discussion related to a comparison performance analysis of all three  AMBA  bus protocol.