AREA OPTIMIZED FSM BASED BIST

Abstract

This paper proposed the structured design methodology to construct FSM based programmable memory BIST approach for testing memory modules in SOC (system on chip). The BIST architecture could be used to test memories in different stage of their fabrication and therefore result in lower overall memory test logic overhead. The proposed scheme supports various memory test algorithms which are used to test different types of memory modules in SOC. We show that proposed FSM based BIST architecture achieves a good flexibility with smaller circuit size compared with previous methods