Review of Vedic Algorithm for OFDM Applications using FIR Filter

Abstract

Digital Filter plays extremely significant role in the domain of Digital Signal Processing (DSP). Multipliers be the important apparatus of system namely, FIR filters, Microprocessors, Digital Signal Processors etc. that demands great results. The working  of these application largely depends on the facts of multiplication done in lesser time. In real time multipliplications the speed and power are the main criterion, therefore the quicker and power proficient multipliers are desirable. Great speed digital telecommunication systems  as OFDM and DSL require real-time high speed calculation. FFT technique be capable of reducing the number of multiplications of a FIR filter base time domain equalizer to a number of analogous to OFDM by the expenditure of delay and reception.  Thus, the filter coefficients is specified with floating point data type but for execution  Field Programmable Gate Array (FPGA) is use to reduce the price, area and power consumption. It is synthesized using Xilinx ISE13.1 for Spartan 3 FPGA board using Vedic multiplier and Distributive Arithmetic architectures for optimal consumption of FPGA resources.