FSM BASED BIST ARCHITECTURE

Abstract

This paper presents a FSM based Programmable Built-In Self-Test (BIST) approach for testing memory modules in SOC(system on chip) In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed BIST   is flexible and selectable. The selection command is used to select a test algorithm from a set of predetermined set of algorithms that are built in memory BIST. By using various memory test algorithm to test different memory module in SOC is scheme greatly simplifies the testing process. We also develop a programmable memory BIST generator that automatically produces RTL model of the proposed BIST architecture for a given set of test algorithms.